A. Technical Field
The present invention relates generally to electronic circuits, and more particularly to short current in standard cell circuits.
B. Background of the Invention
Current circuit design commonly uses standard cell circuits. FIG. 1 is a block diagram of a generalized standard cell circuit 100. Typically, the standard cell circuit 100 includes a pre-driver 104 and a driver 108. An input 102 is coupled to the pre-driver 104. The pre-driver 104 has an output 106 that is coupled to a driver 108. The driver 108 has an output 110.
FIG. 2 shows circuit 200, a specific embodiment of the standard cell circuit 100. In the circuit 200 of FIG. 2, the pre-driver 104 includes a first transistor 202 and a second transistor 204. The input 102 is coupled to the gates of both the first transistor 202 and the second transistor 204. The first transistor 202 is a PMOS transistor and the second transistor 204 is a NMOS transistor. The source of the first transistor 202 is connected to source voltage VDD, and the source of the second transistor 204 is connected to ground GND. The drain of the first transistor 202 is connected to the drain of the second transistor 204, and both drains are coupled to the pre-driver output 106.
The driver 108 includes a third transistor 206 and a fourth transistor 208. The gates of the third transistor 206 and the fourth transistor 208 are connected to the pre-driver output 106. The third transistor 206 is a PMOS transistor and the fourth transistor 208 is a NMOS transistor. The source of the third transistor 206 is connected to source voltage VDD, and the source of the fourth transistor 208 is connected to ground GND. The drain of the third transistor 206 is connected to the drain of the fourth transistor 208. Both the drain of the third transistor 206 and the drain of the fourth transistor 208 are connected to the output 110.
In operation, the circuit 200 shown in FIG. 2 has a short current IS. This short current IS is undesirable because it increases power consumption and produces ground noise.
FIG. 3 shows the circumstances where short current IS occurs in the circuit 200 of FIG. 2. FIG. 3(a) is a graph of the input 102 voltage (xe2x80x9cVINxe2x80x9d) as a function of time. VIN starts low (xe2x80x9cVLOWxe2x80x9d). When VIN is at VLOW, the first transistor 202 is on and the second transistor 204 is off. At a first time 302, VIN begins to transition to high (xe2x80x9cVHIGHxe2x80x9d). At a second time 304, VIN is high enough so that the second transistor 204 begins to turn on. At the second time 304, the first transistor 202 has not turned off. Therefore, since both transistors are at least partially on, current flows directly from the source voltage VDD to the ground GND, resulting in the short current IS.
FIG. 3(b) is a graph of short current as a function of time. As shown in FIG. 3(b), the short current begins to rise at time 304. As VIN continues to transition to VHGH, short current IS continues to flow, peaking at time 306. Finally, at time 308, VIN is high enough (as shown in FIG. 3(a)) for the first transistor 202 to turn off. At this point the short current IS no longer can flow. At time 310, VIN finishes transitioning to VHIGH.
A similar process happens when VIN transitions from VHIGH to VLOW. As shown in FIG. 3(a), between times 310 and 312, VIN is at VHIGH. When VIN is at VHIGH, the first transistor 202 is off and the second transistor 204 is on. At time 312, VIN begins to transition to VLOW. At time 314, VIN is low enough for the first transistor 202 to begin to turn on, and the input is not low enough for the second transistor 204 to have turned off. Therefore, both transistors are again at least partially on, so current flows directly from the source voltage VDD to the ground GND, resulting in the short current IS.
As shown in FIG. 3(b), the short current begins to rise at time 314, as the first transistor 202 has begun to turn on and before the second transistor 204 has turned off. As VIN continues to transition low, short current IS continues to flow, peaking at time 316. Finally, at time 318, VIN is low enough (as shown in FIG. 3(a)) for the second transistor 204 to turn off. At this point the short current IS no longer can flow. At time 50, VIN finishes transitioning to VLOW.
FIGS. 4(a) through 4(d) show other standard cell circuits that suffer the disadvantages of short current IS during operation.
In FIG. 4(a), the circuit 400 is an AND circuit. The AND circuit 400 has a first input 402 and a second input 404. The first input 402 is coupled to the gates of a pair of transistors 412 and 414. Transistor 412 is a NMOS transistor and transistor 414 is a PMOS transistor. The second input 404 is coupled to the gates of a pair of transistors 416 and 418. Transistor 416 is a NMOS transistor and transistor 418 is a PMOS transistor. Transistors 414 and 418 are connected to source voltage VDD and to a pre-driver output 406. Transistor 416 is connected to ground GND and transistor 412, which is in turn connected to the pre-driver output 406. The pre-driver output 406 is connected to the gates of transistors 408 and 410. Transistor 408 is also connected to source voltage VDD and to the output 420. Transistor 410 is also connected to ground GND and to the output 420.
The AND circuit 400 of FIG. 4(a) is affected by short current IS, just as the do circuit 200 of FIG. 2. For example, the pre-driver output 406 transitions between VHIGH and VLOW during use of the AND circuit 400. When such a transition occurs, transistors 408 and 410 are simultaneously on for a period of time, allowing short current IS to flow, as explained above in the discussion of FIGS. 3(a) and 3(b).
In FIG. 4(b), the circuit 430 is an OR circuit. The OR circuit 430 has a first input 432 and a second input 434. The first input 432 is coupled to the gates of a pair of transistors 442 and 444. Transistor 442 is a NMOS transistor and transistor 444 is a PMOS transistor. The second input 434 is coupled to the gates of a pair of transistors 446 and 448. Transistor 446 is a NMOS transistor and transistor 448 is a PMOS transistor. Transistor 444 is connected to source voltage VDD and to transistor 448, which is in turn connected to a pre-driver output 436. Transistors 442 and 446 are connected to ground GND and to pre-driver output 436. The pre-driver output 436 is connected to the gates of transistors 438 and 440. Transistor 438 is also connected to source voltage VDD and to the output 450. Transistor 440 is also connected to ground GND and to the output 450.
The OR circuit 430 of FIG. 4(b) is affected by short current IS, just as the circuit 200 of FIG. 2. For example, the pre-driver output 436 transitions between VHIGH and VLOW during use of the OR circuit 430. When such a transition occurs, transistors 438 and 440 are simultaneously on for a period of time, allowing short current IS to flow, as explained above in the discussion of FIGS. 3(a) and 3(b).
FIGS. 4(c) and 4(d) are a schematic diagram of a D latch 460. The D latch 460 has two inputs, a data input 462 and a clock input 480, and two outputs, Q1 and Q2. The clock input 480 is shown in FIG. 4(d). The portion of the D latch 460 shown in FIG. 4(d) receives the clock input 480 and produces outputs C1 and C2, which are connected to the rest of the D latch 460 at the locations shown in FIG. 4(c).
The D latch 460 of FIGS. 4(c) and 4(d) is affected by short current IS, just as the circuit 200 of FIG. 2. For example, there are numerous transistor pairs 464, 466, 468, 470, 472, 474, and 476 in the D latch. In each of these transistor pairs 464, 466, 468, 470, 472, 474, and 476, the gates of the transistors are connected together. When the voltage at the gates transitions between VHIGH and VLOW during operation of the D latch 460, short current IS will flow through the transistor pairs 464, 466, 468, 470, 472, 474, and 476, as explained above in the discussion of FIGS. 3(a) and 3(b).
FIG. 5 is a block diagram of a previous circuit 500 without the short current problem. The input 502 is coupled to delay 504 and logic 506 circuits. The delay 504 and logic 506 circuits are employed to produce non-overlapping signals driving the gates of the transistors 510 and 512. Transistors 510 and 512 of the circuit 500 of FIG. 5 are analogous to transistors 206 and 208 of the circuit 200 of FIG. 2, which have the problem of short current IS. Since the signals driving the gates of transistors 510 and 512 do not overlap, the transistors 510 and 512 are not both on at any one time, which prevents short current from flowing. Thus, the circuit 500 of FIG. 5 does not have the problem of short current IS. However, the delay 504 and logic 506 circuits of FIG. 5 consume additional power, take up space, and add expense to the circuit.
What is needed is a circuit that reduces short current during operation and does not greatly increase the size or expense over the conventional circuit.
The present invention is a reduced short current circuit that does not greatly increase the size and expense of the circuit over a conventional circuit. A first delay transistor and a second delay transistor are connected to a first transistor and a second transistor to prevent short current through the first and second transistors.
In one embodiment, the first transistor is a PMOS transistor, with its source connected to a source voltage. The second transistor is an NMOS transistor, with its source connected to ground. The first delay transistor is a PMOS transistor, with its source connected to the drain of the first transistor and its drain connected to the drain of the second transistor. The second delay transistor is an NMOS transistor, with its drain connected to the drain of the first transistor and its source connected to the drain of the second transistor. The gates of the first transistor, the second transistor, the first delay transistor, and the second delay transistor are connected together.
In another embodiment, the first transistor is a PMOS transistor, with its source connected to a source voltage. The second transistor is a NMOS transistor, with its source connected to ground. The drain of the first transistor is connected to the drain of the second transistor. The first delay transistor is a PMOS transistor, with its source connected to the gate of the first transistor and its drain connected to the gate of the second transistor. The second delay transistor is a NMOS transistor, with its drain connected to the gate of the first transistor and its source connected to the gate of the second transistor.